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A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA
Weixiong Jiang,
Heng Yu
, Yajun Ha
School of Computer Science
Research output
:
Journal Publication
›
Article
›
peer-review
4
Citations (Scopus)
Overview
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Keyphrases
8-bit
20%
Accuracy Loss
20%
Computing Resource Allocation
20%
Dataflow Architecture
60%
Edge Computing Applications
20%
Feature Map
40%
FPGA Acceleration
20%
High-throughput
100%
Integer Quantization
40%
Intermediate Features
20%
Latency
20%
Lightweight Neural Network
20%
Memory Resource
20%
MobileNetV2
100%
On-chip Memory
20%
Parallelization
20%
Quantization Accuracy
20%
Residual Connection
20%
Resource Allocation Strategy
40%
Xilinx
20%
ZCU102
20%
Computer Science
Allocation Strategy
40%
Computing Resource
20%
Edge Computing
20%
Experimental Result
20%
High Throughput
100%
Memory Resource
20%
MobileNetV2
100%
Neural Network
20%
Parallelism
20%
Quantization (Signal Processing)
60%
Resource Allocation
40%