A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps

Keyphrases

• Application Specific Integrated Circuits 100%
• Area Usage 20%
• Array Architecture 20%
• Circuit Area 20%
• Cycle-level 20%
• Dynamic Power Consumption 20%
• Dynamic Reconfiguration 40%
• Dynamically Reconfigurable 20%
• Dynamically Reconfigurable Architecture 100%
• Field Programmable Gate Arrays 100%
• Hardware Resources 20%
• Hybrid CMOS 20%
• Large Delay 20%
• Level Dynamics 20%
• Logic Density 20%
• Logic Element 40%
• Logic Folding 80%
• Long Distance 20%
• Nanotechnology 40%
• New Architecture 20%
• On-chip Communication 20%
• Order of Magnitude 20%
• Power Gap 20%
• Reconfigurable Architectures 40%
• Reconfigurable Logic 20%
• Reconfiguration 20%
• Silicon Area 20%
• Static RAM 20%
• Temporal Logic 20%

Engineering

• Application Specific Integrated Circuit 100%
• Array Architecture 20%
• Bridging 20%
• Dynamic Reconfiguration 40%
• Electric Power Utilization 20%
• Field Programmable Gate Arrays 100%
• Fine Grain 100%
• Interconnects 40%
• Lookup Table 20%
• Reconfigurability 20%
• Reliability Availability and Maintainability (Reliability Engineering) 20%

Computer Science

• Application Specific Integrated Circuit 100%
• Dynamic Power Consumption 20%
• Dynamic Reconfiguration 40%
• Field Programmable Gate Arrays 100%
• Full Advantage 20%
• Hardware Resource 20%
• Logic Element 40%
• reconfigurable architecture 100%
• Reconfigurable Logic 20%
• Table Lookup 20%
• Temporal Logic 20%