Minimization of network induced jitter impact on FPGA-based control systems for power electronics through forward error correction

Valentina Bianchi, Filippo Savi, Ilaria De Munari, Davide Barater, Giampaolo Buticchi, Giovanni Franceschini

Research output: Journal PublicationArticlepeer-review

4 Citations (Scopus)

Abstract

In modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on machine drives distributed control, caused by the messages’ re-transmission in case of an error in the received data. To achieve this goal, two different Forward Error Correction (FEC) techniques are introduced in the chosen protocol, so that the recipient of the message can correct random errors without the need of any additional round trip delays needed to request and obtain a re-transmission. Experimentally validated simulations are used to evaluate the impact of random network derived jitter on a real world closed loop control system for distributed power electronic converters.

Original languageEnglish
Article number281
JournalElectronics (Switzerland)
Volume9
Issue number2
DOIs
Publication statusPublished - Feb 2020

Keywords

  • Digital communications
  • Error correction codes
  • Faulttolerance
  • Field programmable gate array (FPGA)
  • Modular power converters

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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