TY - GEN
T1 - FPGA implementation of a configurable viterbi decoder for software radio receiver
AU - Shaker, Sherif Welsen
AU - Elramly, Salwa Hussien
AU - Shehata, Khaled Ali
PY - 2009
Y1 - 2009
N2 - Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.
AB - Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.
KW - FPGA
KW - Software defined radio
KW - VHDL
KW - Viterbi decoder
UR - http://www.scopus.com/inward/record.url?scp=72249105736&partnerID=8YFLogxK
U2 - 10.1109/AUTEST.2009.5314063
DO - 10.1109/AUTEST.2009.5314063
M3 - Conference contribution
AN - SCOPUS:72249105736
SN - 9781424449811
T3 - AUTOTESTCON (Proceedings)
SP - 140
EP - 144
BT - IEEE AUTOTESTCON 2009 Proceedings
T2 - IEEE AUTOTESTCON 2009 - Systems Readiness Technology Conference: Mission Assurance Through Advanced ATE
Y2 - 14 September 2009 through 17 September 2009
ER -