TY - GEN
T1 - A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis
AU - Chun, Hosung
AU - Tran, Nhan
AU - Yang, Yuanyuan
AU - Kavehei, Omid
AU - Bai, Shun
AU - Skafidas, Stan
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2012
Y1 - 2012
N2 - In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator front-end to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476μA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.
AB - In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator front-end to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476μA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.
UR - http://www.scopus.com/inward/record.url?scp=84882944289&partnerID=8YFLogxK
U2 - 10.1109/EMBC.2012.6346595
DO - 10.1109/EMBC.2012.6346595
M3 - Conference contribution
C2 - 23366556
AN - SCOPUS:84882944289
SN - 9781424441198
T3 - Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS
SP - 3001
EP - 3004
BT - 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2012
T2 - 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS 2012
Y2 - 28 August 2012 through 1 September 2012
ER -