Fault tolerant distributed drive for multiphase machines

Abstract

The aim of this work is to explore the needs, in terms of power electronics and control of high power fault-tolerant machine drive when used in mission critical aerospace applications.
Much work has already been done to develop high performance electrical machines and converter topologies, making large gains in these fields less likely. The architectural and control levels on the other hand have been much less explored, making an in depth, system level study of these topics worthwhile.
The main focus throughout the whole design process has been total scalability of the designed architecture, achieved through vertically integrated co-design of power electronics hardware, firmware and software. In this thesis a distributed fault-tolerant drive architecture is presented, potentially able to scale effortlessly up to hundreds of phases, without significant redesign.
Few key technologies enabling high frequency distributed current control in a scalable system have been developed. A custom communication protocol has been introduced, designed from the ground up for distributed power electronics control applications, enabling sub microsecond communication latency on bandwidth limited channels, like common and cheap plastic optical fibres.
Being tailored to the specific application it also avoids the common pitfalls related to the industrial automation origins of the most common protocols.

A second cornerstone of the architecture, introduced in this thesis, are a custom Instruction Set Architecture (ISA) and the related processing core, tailored to perform control system calculations with total determinism, as opposed to the commonly used Discrete DSP processors. Their implementation inside an FPGA combines the advantages of both systems, with scalability and determinism proper of custom logic, while retaining the ease of development typical of software systems.
Finally, a highly scalable synchronous reference frame current control strategy is adopted, in order to take full advantage of the designed distributed drive architecture. The avoidance of commonly used reference frame
transformations completely decouples the implementation of current controllers between phases, enabling parallelization of the entire control system, that channels, in case of necessity, be partitioned across multiple computing nodes, without the strict need for high speed communication links between them.

Date of Award	Jul 2022
Original language	English
Awarding Institution	University of Nottingham
Supervisor	Chris Gerada (Supervisor), Giampaolo Buticchi (Supervisor) & Pat Wheeler (Supervisor)