Tighter WCET analysis of input dependent programs with classified-cache memory architecture

Li Yanhui, Shakith Devinda Fernando, Yu Heng, Chen Xiaolei, Ha Yajun, Tiow Tay Teng

Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

Abstract

Caches in Embedded Systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches. This is a critical problem in real-time systems, where tight Worst Case Execution Time (WCET) is required for their schedulability analysis. Several works have studied the data cache impacts on the WCET of programs, but they can only handle programs with no input dependent data accesses. To solve this problem, we have developed a novel architecture and a WCET analysis framework for this architecture. Our work classifies predictable and unpredictable accesses and allocates them into predictable caches and unpredictable caches respectively, using the CME (Cache Miss Equations) and reuse-distance based algorithms accordingly. The analysis framework produces a very good WCET tightness compared with simulations, and our architecture creates almost no hardware overhead or performance degradation.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages410-413
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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