Simulation of junctionless Si nanowire transistors with 3 nm gate length

Lida Ansari, Baruch Feldman, Giorgos Fagas, Jean Pierre Colinge, James C. Greer

Research output: Journal PublicationArticlepeer-review

98 Citations (Scopus)


Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼1 nm wire diameter and ∼3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.

Original languageEnglish
Article number062105
JournalApplied Physics Letters
Issue number6
Publication statusPublished - 9 Aug 2010
Externally publishedYes

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)


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