FPGA implementation of a configurable viterbi decoder for software radio receiver

Sherif Welsen Shaker, Salwa Hussien Elramly, Khaled Ali Shehata

Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

Original languageEnglish
Title of host publicationIEEE AUTOTESTCON 2009 Proceedings
Pages140-144
Number of pages5
DOIs
Publication statusPublished - 2009
Externally publishedYes
EventIEEE AUTOTESTCON 2009 - Systems Readiness Technology Conference: Mission Assurance Through Advanced ATE - Anaheim, CA, United States
Duration: 14 Sep 200917 Sep 2009

Publication series

NameAUTOTESTCON (Proceedings)

Conference

ConferenceIEEE AUTOTESTCON 2009 - Systems Readiness Technology Conference: Mission Assurance Through Advanced ATE
Country/TerritoryUnited States
CityAnaheim, CA
Period14/09/0917/09/09

Keywords

  • FPGA
  • Software defined radio
  • VHDL
  • Viterbi decoder

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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