FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Ting Jung Lin, Wei Zhang, Niraj K. Jha

Research output: Journal PublicationArticlepeer-review

7 Citations (Scopus)


Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the area-delay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by 3.6× compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective area-delay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

Original languageEnglish
Article number6939705
Pages (from-to)1987-2000
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
Publication statusPublished - Oct 2015
Externally publishedYes


  • Dynamic reconfiguration
  • field-programmable gate arrays
  • integrated circuits
  • logic folding

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation'. Together they form a unique fingerprint.

Cite this