Abstract
Empowered by Large Language Models (LLMs), substantial progress has been made in enhancing the EDA design flow in terms of high-level synthesis, such as direct translation from high-level language into RTL description. On the other hand, little research has been done for logic synthesis on the netlist generation. A direct application of LLMs for netlist generation presents additional challenges due to the scarcity of netlist-specific data, the need for tailored fine-tuning, and effective generation methods. This work first presents a novel training set and two evaluation sets catered for direct netlist generation LLMs, and an effective dataset construction pipeline to construct these datasets. Then this work proposes LLM4NETLIST, a novel step-based netlist generation framework via fine-tuned LLM. The framework consists of a step-based prompt construction module, a fine-tuned LLM, a code confidence estimator, and a feedback loop module, and is able to generate netlist codes directly from natural language functional descriptions. We evaluate the efficacy of our approach with our novel evaluation datasets. The experimental results demonstrate that, compared to the average score of the 10 commercial LLMs listed in our experiments, our method shows a functional correctness increase of 183.41% on the NetlistEval dataset and a 91.07% increase on NGen.
| Original language | English |
|---|---|
| Pages (from-to) | 337-348 |
| Number of pages | 12 |
| Journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
| Volume | 15 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - May 2025 |
Free Keywords
- circuit design
- electronic design automation
- large language model
- natural language processing
- netlist generation
ASJC Scopus subject areas
- Electrical and Electronic Engineering