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Common-mode voltage mitigation of dual three-phase voltage source inverters in a motor drive application

  • Abraham Marquez Alcaide
  • , Xuchen Wang*
  • , Hao Yan
  • , Jose I. Leon
  • , Vito Giuseppe Monopoli
  • , Giampaolo Buticchi
  • , Sergio Vazquez
  • , Marco Liserre
  • , Leopoldo G. Franquelo
  • *Corresponding author for this work

Research output: Journal PublicationArticlepeer-review

133 Downloads (Pure)

Abstract

Electric variable speed drives (VSDs) based on two VSDs connected to a multiphase machine are an attractive solution to replace high-power mechanic and hydraulic systems in many sectors of industry and transportation because they present high performance with reduced cost, volume and weight. Among the causes which affect the reliability of dual VSDs, the common-mode current flowing through the machine bearing is an important issue. This paper faces the mitigation of the common-mode current by reducing the common-mode voltage (CMV) generated by the operation of a dual VSD. The CMV reduction is carried out without introducing any extra device and/or passive filtering method. This CMV reduction is performed by applying a specific phase-displacement between the modulation strategies of each single inverter drive. The proposed technique has been evaluated in a down scaled experimental setup in order to test its effectiveness
Original languageEnglish
Article number9402840
Pages (from-to)67477-67487
Number of pages11
JournalIEEE Access
Volume9
DOIs
Publication statusPublished - 13 Apr 2021

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

  1. SDG 11 - Sustainable Cities and Communities
    SDG 11 Sustainable Cities and Communities

Free Keywords

  • Harmonic analysis
  • common-mode voltage
  • pulse width modulation

ASJC Scopus subject areas

  • General Computer Science
  • General Materials Science
  • General Engineering

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