An Efficient Statistical Clock Skew Analysis Method for Clock Trees

Increasing process variability poses great challenge in 2D/3D high-performance clock network design. The variation of device, interconnect and TSV lead to the clock skew variation. However, in most prior models, the variation was not considered comprehensively, where the effect of the equivalent capacitance variation of the interconnect/TSV on the delay of the device was ignored, leading to poor accuracy for clock tree delay variation. In this work, an efficient statistical clock skew analysis method for clock trees is proposed, which considers the variations of device, interconnect, and TSV in 2D/3D clock trees together, and considers the cap variation impact on device variation during the bottom up propagation algorithm. The proposed model was validated under TSMC 22nm process by 3D clock trees implemented for artificial H-tree constructed cases and ISCAS'89 benchmarks. Our model demonstrates excellent agreement with golden Monte Carlo simulation results in terms of the standard deviation of maximum clock skew with the average error of 2.47% while achieves 1400 times speed up. Comparing with competitive works, our model achieves 1.9 times accuracy improvement with comparative simulation effort.