Abuttable Analog Cell Library and Automatic AMS Layout

The state-of-the-art analog circuit design applies mainly a full-custom layout methodology. This demands high expertise and heavy manual workload. Additionally, neither can the resulting layout be re-used easily across different designs or different PDKs. Learning from digital standard cells, existing work has proposed analog stem cells that are abuttable. But stem cells have a fixed 2× area overhead of same-sized Pcells, limiting their wide application. In this paper we develop a new type of abuttable analog cells (called Acells) for transistors and passive elements. Acells are compatible with digital standard cells and can be abutted in all directions, enabling the use of automatic digital place and route (PnR) engines. We automate Acell generation and show that the average area ratio over same-sized Pcell is 1.49 for 65nm technology and 1.3 for 28nm technology, and is expected to decrease for more advanced technologies. We then use digital PnR to automatically generate layout of several analog and mixed-signal (AMS) circuits mainly in 28nm. Compared to Pcell-based manual layout, Acell-based layout obtains similar performance and its circuit-level layout area is about 2% higher for large scale AMS circuits in our experiments.